Lead IP/SoC level design verification

Overview:

ADVANCE YOUR CAREER. ADVANCE THE WORLD.

At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future.

Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger - technology that moves the world forward. Join us and, together, we’ll advance your career.

Responsibilities:

THE ROLE:

The focus of this role is to plan, build, and execute the verification of new and existing features for AMD's Soft IP cores, ensuring high-quality,silicon-proven IP delivered across supported platforms with zero escapes to

production.

THE PERSON:

You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.

KEY RESPONSIBILITIES:

Collaborate with IP designers, architects, and application engineers to understand new features and parameterization requirements to be verified

Develop comprehensive verification strategies including:

Test plans and functional coverage models

Assertion-based verification (ABV)

Constrained-random verification

Formal verification where applicable

Build comprehensive test plan documentation covering functional coverage, parameter space, platform interactions, and end-user use cases

Estimate effort required to develop new feature tests and any updates needed to the verification environment

Develop directed and constrained-random verification tests, including parameter configuration and coverage closure strategies

Drive verification closure using coverage metrics, bug convergence, and quality sign-off criteria

Debug complex design and verification issues spanning digital and firmware interfaces

Review verification architecture, testbench design, and coding standards across the team

Build comprehensive test plan documentation covering functional coverage, parameter space, platform interactions, and end-user use cases

Estimate effort required to develop new feature tests and any updates needed to the verification environment

Drive adoption and continuous improvement of:

UVM methodology and System Verilog best practices

Assertion-based verification flows

Regression infrastructure and CI/CD verification flows

Coverage-driven verification strategies

AI-assisted verification productivity tools

Verification automation frameworks

Promote IP reuse and standardized verification environments across projects

Maintain and improve nightly regression infrastructure across all supported platforms and configurations

Contribute to IP quality sign-off reviews and pre-release validation

PREFERRED EXPERIENCE:

10+ years of industry experience in IP/SoC level design verification

Proficient in IP-level ASIC or FPGA functional verification

Proficient in debugging RTL using industry-standard simulation tools (Questa, Xcelium, VCS, Vivado Simulator)

Proficient in UVM-based testbench development and constrained-random verification methodologies

Strong hands-on experience with:

SystemVerilog and UVM verification frameworks

Assertion-based verification (SVA, PSL)

Functional and code coverage closure

Formal verification tools and methodologies

Experience developing and maintaining verification frameworks, regression flows, and CI/CD verification pipelines

Automating workflows in distributed compute environments (LSF or equivalent)

Exposure to AI-assisted verification tools and automation frameworks

Exposure to simulation acceleration, coverage-driven verification, and formal verification techniques

Scripting experience: Python, Perl, shell, Makefile preferred

Exposure to leadership or mentorship is an asset

Prior experience with high-speed interface protocols is a strong plus, including:

Video/Display: HDMI, DisplayPort (DP), MIPI DSI/CSI

Connectivity: USB 3.x/4.0, PCIe Gen 4/5, Ethernet (1G/10G/25G/100G)

Memory interfaces: DDR4/DDR5, LPDDR4/LPDDR5

On-chip interconnects: AXI, AHB, APB

SerDes and PHY-level protocol verification experience

ACADEMIC CREDENTIALS:

Bachelors or Masters degree in computer engineering/Electrical Engineering

#LI-SR4

Qualifications:

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.