SoC Design Verification Engineer

Job Details:

Job Description:

Do Something Wonderful. Intel put the Silicon in Silicon Valley. No one else is this obsessed with engineering a brighter future. Every day, we create world changing technology that enriches the lives of every person on earth. So, if you have a big idea, let's do something wonderful together. Join us, because at Intel, we are building a better tomorrow.

Come join us -In this role you will be part for the Server SoC Design Validation team, working on next-generation Xeon server product SOCs and IPs.

Your responsibilities include but are not limited to:

Performs functional logic verification and emulation validation of an integrated SoC to ensure design will meet specifications.

Defines and develops scalable and reusable block, subsystem, and SoC verification plans, test benches, and the verification environment to meet the required level of coverage and confirm to microarchitecture specifications.

Executes verification plans and defines and runs emulation and system simulation models to verify the design, analyze power and performance, and uncover bugs.

Replicates, root causes, and debugs issues in the pre-silicon environment. Finds and implements corrective measures to resolve failing tests.

Collaborates and communicates with SoC architects, micro-architects, full chip architects, RTL developers, post-silicon, and physical design teams to improve verification of complex architectural and microarchitectural features.

Documents test plans and drive technical reviews of plans and proofs with design and architecture teams.

Incorporates and executes security activities within test plans, including regression and debug tests, to ensure security coverage.

Maintains and improves existing functional verification infrastructure and methodology.

Absorbs learning from post-silicon on the quality of validation done during pre-silicon development, updates test plan for missing coverages and proliferates to future products.

Behavioral traits that we are looking for Robust understanding of fundamental principles of cache coherency in multi-processor SOCs, and experience with layered protocols - transaction layer, data link layer, and PHY layer.

Strong debug skills and self-reliance in taking an issue to closure with internal and external partners.

Takes ownership of assigned tasks.

Keen problem solver, strong communicator, quick learner, effective team player and open to learning and teaching new and more efficient validation execution techniques to meet time-to-market.

Qualifications:

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your degree, research and or relevant previous job and or internship experiences.

Minimum Qualifications:

Bachelors degree in Electrical or Computer Science, Engineering or related field with 1 year plus of related technical experience OR Masters Degree in Electrical or Computer Science, Engineering or related field OR PhD in Electrical or Computer Science, Engineering or related field.

Related coursework/technical experience in/with: Silicon Design and/or Validation/Verification.

Preferred Qualifications:

Design and/or Design Verification with developing, maintaining, and executing complex IPs and/or SOCs.

UVM/SV constrained-random coverage-based design verification.

OVM/VM/UVM, System Verilog, constrained random verification methodologies.

Complete verification life cycle (verification architecture, test plan, execution, debug, coverage closure).

Developing validation test suites and driving continuous improvement into existing validation test suites and methodologies.

UVM/SV Verification IP architecture, development and validation experience.

Xeon CPU Pre-Silicon, Emulation Validation or Post Silicon Validation.one or more scripting languages to facilitate automation.

Experience would be obtained through a combination of prior education level classes, and current level school classes, projects, research, and relevant previous job and/or internship experience.

Job Type:

College Grad

Shift:

Shift 1 (United States of America)

Primary Location:

US, California, Santa Clara

Additional Locations:

Posting Statement:

Position of Trust

N/A

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel .

Annual Salary Range for jobs which could be performed in the US: $105,650.00-172,860.00 USD

The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.