MSIP PLL Design Verification Engineer, Sr Lead

Company:

Qualcomm India Private Limited

Job Area:

Engineering Group, Engineering Group > Hardware Engineering

General Summary:

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.

Minimum Qualifications:

Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.

OR

Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

OR

PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.

Join Qualcomm's design verification team in verifying the high-speed mixed-signal IP designs (PLL, DAC, ADC, Sensors, PCIe, USB, MIPI, CXL, C2C, D2D, DDR, etc.) for exciting products targeted for 5G, AI/ML, compute, IOT, and automotive applications. The team is responsible for the complete design verification lifecycle, from system-level concept to tape out and post-silicon support.

Responsibilities:

Define pre-silicon and post-silicon testplans based on design specs and using applicable standards working closely with design team.

Architect and develop the testbench using advanced verification methodology such as SystemVerilog/UVM, Functional Verification, UPF / Low power verification, Formal verification and Gate level simulation to ensure high design quality.

Author assertions in SVA, develop testcases, coverage models, debug and ensure coverage closure.

Work with digital design, analog circuit design, modeling, controller/subsystem, & SoC integration teams to complete the successful PHY level verification, integration into subsystem and SoC, and post-silicon validation.

Minimum Qualifications:

Master's/Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field.

5+ years ASIC design verification, Pre Silicon Verification or related work experience.

Knowledge of a HVL methodology like SystemVerilog/UVM.

Experience working with various ASIC simulation/formal tools such as VCS, Xcellium/NCsim, Modelsim/Questa, VCFormal, Jaspergold, 0In and others.

Preferred Qualifications:

Experience with Pre Silicon Verification, Low power design verification, Formal verification and Gate level simulation at IP/SS level.

Experience in scripting languages (Python, or Perl).

Experience with mixed-signal IP design verification, such as USB, PCIe, CXL, C2C, D2D, MIPI, UFS, DDR, PLL, Data Convertors (DAC, ADC), or sensors will be an added advantage.

Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.

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