Campus-Beginner

Hubli, Karnataka

Job Summary

We are looking for enthusiastic and technically sound Designer – Analog Layout Design candidates who have completed formal training or internship programs in VLSI Analog Layout Design. The candidate will work under the guidance of experienced layout engineers and contribute to the physical implementation of Analog, Mixed-Signal, and Custom Layout blocks.

The role offers an excellent opportunity to learn industry-standard design methodologies, semiconductor process technologies, physical verification flows, and advanced layout implementation techniques while working on real customer projects and product development programs. Training programs within the organization emphasize CMOS fundamentals, IC fabrication, Cadence-based Analog Layout Design, and project-oriented learning.

Key Responsibilities

Analog Layout Implementation

Support the creation of custom layouts for analog and mixed-signal circuits.

Assist in layout development for:

Amplifiers

Current Mirrors

Comparators

LDOs

Bandgap Circuits

Level Shifters

Oscillators

DACs

Analog Sub-blocks

Learn and apply standard analog layout methodologies during implementation activities. Experience summaries from junior layout engineers indicate exposure to blocks such as OPAMPs, current mirrors, level shifters, LDOs, and amplifiers as part of early-career responsibilities.

Floorplanning & Routing

Support floorplanning activities based on design constraints.

Perform device placement and routing under technical supervision.

Learn routing techniques for analog signal integrity, shielding, and power distribution.

Gain understanding of area optimization and layout quality requirements. Entry-level layout profiles reference floorplanning, placement, routing, and top-level integration activities.

Physical Verification

Perform basic physical verification checks including:

DRC

LVS

Antenna Checks

Density Checks

Analyze and fix verification violations with guidance from senior engineers.

Understand verification sign-off criteria and layout quality requirements. Verification activities such as DRC, LVS, density checks, and related quality checks are identified as foundational responsibilities in internal layout profiles and training material.

Design Quality & Learning

Learn layout best practices including:

Device Matching

Common Centroid Structures

Symmetry

Guard Rings

Shielding

Develop understanding of semiconductor manufacturing constraints and layout-dependent effects.

Participate in technical reviews, training sessions, and knowledge-sharing activities. Internal training programs specifically emphasize CMOS fundamentals, fabrication concepts, and Analog Layout Design practices.

Team Collaboration

Work closely with layout engineers, circuit designers, and technical leads.

Participate in project discussions and review meetings.

Support project execution activities while adhering to quality and schedule commitments.

Skill Requirements

Mandatory Skills

Understanding of Analog and Mixed-Signal circuit fundamentals.

Basic knowledge of:

CMOS Devices

Semiconductor Fabrication

Electronic Circuits

Layout Design Concepts

Exposure to:

Floorplanning

Device Placement

Routing

Physical Verification

Good understanding of analog layout concepts such as:

Matching

Symmetry

Shielding

Guard Rings

Strong willingness to learn and adapt to customer-specific methodologies. Internal Analog Layout training programs emphasize CMOS fundamentals, fabrication knowledge, geometric aptitude, and Analog Layout Design using Cadence flow.

Preferred Skills

Internship or training project experience involving:

Analog Layout Design

Custom Layout Design

Mixed-Signal Layout Design

Exposure to advanced technology nodes through training projects.

Basic scripting knowledge is an added advantage. Automation exposure through SKILL, Shell, and scripting forms part of internal training curricula.

EDA Tools Exposure

Candidates should have academic, internship, or training exposure to one or more of the following:

Cadence Virtuoso

Calibre

Assura

PVS

Layout Verification Tools

Other Requirements

Cadence-based Analog Layout Design and physical verification flows are specifically highlighted in internal training programs and engineer profiles.

Educational Qualification

B.E. / B.Tech. in:

Electronics & Communication Engineering

Electrical & Electronics Engineering

Electronics Engineering

Instrumentation Engineering

OR

M.Tech. / M.E. in:

VLSI Design

Microelectronics

Semiconductor Technology

Embedded Systems

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