Sr. Staff Analog Design Engineer

About SiTime

SiTime is the Precision Timing company.

Timing is the heartbeat of all electronics, ensuring performance, resilience and scalability. For decades, quartz devices, non-silicon technology, have kept systems in sync, but they struggle in harsher, more demanding environments. MEMS-based Precision Timing delivers greater accuracy, smaller size and resilience. Today, MEMS timing powers over 400 applications, including high-growth ones in AI datacenters, automated driving, industrial and humanoid robots, wearables and IoT.

Our semiconductor MEMS programmable solutions offer a rich feature set that enables customers to differentiate their products with higher performance, smaller size, lower power, and better reliability. With more than 4 billion devices shipped, SiTime is changing the timing industry. For more information, visit: www.sitime.com.

Job Summary

SiTime is seeking a Senior Staff Analog Design Engineer to provide technical leadership in developing advanced clock and timing products. This role combines hands-on circuit design expertise with strong system-level understanding to balance performance, schedule, and cost trade-offs. Working closely with test and validation, program management, product engineering, and other functional teams, you will align technical solutions with business goals and drive projects from concept through successful execution in a collaborative, fast-paced environment.

Responsibilities:

Define, design, and develop innovative circuits for high-performance timing products

Mentor, lead, and guide junior designers

Collaborate effectively with remote engineering teams

Support prototype testing, debugging, and lab characterization

Provide technical support across the full product development cycle through production release

Qualifications & Requirements:

Master’s or PhD degree in Electrical Engineering

10+ years of relevant experience in analog/mixed-signal CMOS design

Strong knowledge of integrated circuit design, device physics, and process technology

Experience designing PLLs or related building blocks, including VCOs, phase detectors, charge pumps, and similar circuits

Deep understanding of transistor behavior, circuit noise theory, and phase noise concepts

Proficiency with the Cadence analog/mixed-signal simulation toolset

Familiarity with analog/mixed-signal design flow, simulation methods, design rules, post-layout verification

Experience with analog behavioral modeling using SystemVerilog, Verilog-A, or AMS

Hands-on experience with lab testing and characterization

It is not necessary to meet all job requirements to be a qualified candidate for the position.

Desired Characteristics & Attributes:

Collaborative, self-motivated, and positive team contributor

Able to empower others and provide effective mentorship

Strong analytical and problem-solving skills

Compensation Range:

At SiTime, we believe great work deserves great rewards. We offer a comprehensive and highly competitive compensation package designed to attract top talent.

The annual base salary range for this role is CAD$130,500 to 186,620. The final offer is determined by factors such as location, experience, education, and training.

In addition to base salary, this role is eligible for a quarterly bonus tied to the achievement of innovation goals - reflecting our commitment to recognizing meaningful impact. We also offer equity grants, providing a meaningful opportunity to share in the company’s future growth and success.

Learn More about SiTime: Review the Get to Know SiTime section of our career page to explore our culture, values, and what makes us unique.

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SiTime Corporation – YouTube

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