Design Verification Engineer

Key Responsibilities:

Build constrained-random verification environments using SystemVerilog, UVM, and SVA.

Extract test plans from specifications; write block and chip-level tests using C, SV, and UVM.

Debug complex RTL and gate-level simulations alongside design engineers.

Develop diagnostic tests for pre-tapeout FPGA prototypes and post-silicon ASIC validation.

Replicate post-silicon issues in simulation to prove out RTL fixes or software workarounds.

Convert verification suites into ATE vectors and assist with initial tester bring-up.

Automation-first mindset: develop custom scripts to optimize verification velocity and evaluate modern EDA tools/methodologies.

Pay: $80.00 - $94.00 per hour

Benefits:

401(k) matching

Dental insurance

Health insurance

Health savings account

Paid time off

Work Location: In person