unknown$156k-$166k/yrPosted Jul 9, 2026
Posting intelligenceActively listed

About the role

The task includes RTL design using Verilog HDL, with a focus on implementation and debugging.

Comprehend the architectural specification at the System on Chip level.

Draft the microarchitecture guidelines for the newly introduced and updated functionalities. Charge includes design linking and simulation.

Collaborate with the synthesis and backend teams for the physical implementation.

Master's or Bachelor's degree in Computer Engineering is required.

10 years plus of professional experience

Pay: $75.00-$80.00 per hour

Work Location: In person

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