Mixed Signal Logic Design Engineer

Job Details:

Job Description:

Qualifications:

Minimum Qualifications - Bachelor's or Master's degree in Electrical or Computer Engineering, or a closely related field. - 4-12 years of experience with a Bachelor's degree or 3-10 years of experience with a Master's degree. - Strong expertise in RTL development using System Verilog. - Proficiency in low-power design techniques, including UPF, clock gating, and multiple clock domain design. - Hands-on experience with front-end design tools such as Spyglass, VC Lint, CDC, and synthesis tools. - Solid understanding of state machine design, simulation, and debugging using tools like VCS and Verdi. - Scripting proficiency in Perl, Python, or TCL for design automation and workflow optimization. Preferred Qualifications - Familiarity with DFI, DDR, or LPDDR protocols and DDR PHY/Memory Controller designs. - Basic understanding of analog design to facilitate optimal integration of analog and digital components. - Pre-silicon and post-silicon validation experience is an advantage. - Knowledge of area and power optimization techniques for IP designs. - Strong problem-solving skills with the ability to make critical technical decisions in complex situations. Join us in redefining the boundaries of technology and innovation. Apply today to be part of a team that drives transformative solutions for tomorrow's challenges.

Job Type:

Experienced Hire

Shift:

Shift 1 (India)

Primary Location:

India, Bangalore

Additional Locations:

Business group:

The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.

Posting Statement:

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.