Analog Design - Staff Engineer

Date posted 07/08/2026

Category Engineering Hire Type Employee Job ID 18037 Remote Eligible No Date Posted 07/08/2026

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent years in the trenches of analog design, working on circuits that move data at speeds most people cannot fathom. SerDes is not just a buzzword to you, it is the domain where you have built voltage-mode drivers, tuned PLLs until they locked cleanly, and debugged equalization schemes that looked perfect in simulation but needed three more iterations in layout. You know that a well-designed CDR is the difference between a link that works and one that fails margin at the customer site.

You do not wait for a reference design to be handed to you. When you see a spec, you already start sketching topologies and thinking through tradeoffs between power, area, and performance. Layout is not something that happens after you finish the schematic, it is part of your design process from day one. A long metal run or poor device placement catches your eye in a floorplan review because you know exactly how it will show up in post-layout simulation.

At Synopsys, you will work on SerDes IP that ships in AI accelerators, data center switches, automotive SoCs, and consumer electronics. The circuits you design will be measured in gigabits per second, and the decisions you make will matter in millions of devices.

What You'll Be Doing

Design and optimize analog front-end building blocks for SerDes IP, including voltage and current-mode drivers, equalizers (CTLE, FFE, DFE), CDR circuits, PLLs, DLLs, VCOs, phase interpolators, bandgaps, and regulators

Run SPICE simulations across PVT corners and create verification test benches that validate performance against PCIe 6.0, PCIe 7.0, PAM4, Ethernet, USB, HDMI, or other high-speed protocol specifications

Collaborate closely with layout engineers to minimize parasitic resistance and capacitance, reduce mismatch, and account for proximity effects in sub-micron CMOS processes

Work with digital RTL engineers to verify calibration loops, adaptation algorithms, and control logic that tune your analog circuits in real time

Present simulation results, design tradeoffs, and performance data in peer reviews and customer-facing technical discussions

Document circuit architecture, design features, verification strategies, and test plans for integration into larger SerDes products

Own the full lifecycle of your blocks from spec to silicon, including post-layout verification, characterization support, and design-for-reliability checks for electromigration, IR drop, aging, and ESD

The Impact You Will Have

Your circuits will enable multi-gigabit data transfer in AI accelerators, data center switches, automotive SoCs, and consumer electronics shipping in millions of units

You will help Synopsys deliver SerDes IP that meets the performance and power targets our customers depend on to win in competitive markets

Your layout optimization and simulation rigor will reduce respins, saving months of schedule and significant engineering cost

The verification strategies you define will catch corner-case failures before tapeout, improving first-pass silicon success rates

Your collaboration with digital and system teams will ensure analog-digital co-design works seamlessly, not just in theory but in real integrated test chips

You will contribute to the technical foundation of next-generation high-speed standards, influencing how the industry builds faster, more efficient links

Your documentation and knowledge sharing will raise the design quality and speed of the entire analog team

What You'll Need

PhD with 2+ years of hands-on SerDes or high-speed analog design experience, or BTech/MTech with 5 to 10 years in the same domain

Silicon-proven experience designing and bringing up analog or mixed-signal blocks in production chips, you have seen your circuits work in real silicon

Deep expertise in at least several of these building blocks: analog front-end transceivers, voltage/current-mode drivers, PLLs, DLLs, VCOs, CDR circuits, bandgaps, regulators, CTLE, FFE, DFE, impedance calibrators, serializers, deserializers, or phase interpolators

Strong proficiency with SPICE simulation tools and sub-micron CMOS design methodologies, you know how to set up corners, sweep parameters, and interpret results that matter

Experience optimizing layout for performance, including parasitic extraction, device matching, stress effects, and design-for-reliability considerations like electromigration, IR drop, and aging

Familiarity with scripting languages such as TCL or Perl for automation and simulation flow setup is a strong plus

Working knowledge of high-speed serial standards like PAM4, PCIe 6.0, PCIe 7.0, Ethernet, USB, SATA, HDMI, or MIPI is highly valued

Who You Are

You can take a specification document and translate it into a circuit architecture without waiting for someone to hand you a reference design

You catch layout issues early, you review floorplans and flag where a long metal run or poor device placement will degrade performance before it becomes a post-layout surprise

You are comfortable presenting technical data to peers and customers, you can walk someone through a Bode plot or an eye diagram and explain what it means for margin and yield

You push back when a requirement does not make sense or when a verification plan has gaps, you care about getting it right more than checking a box

You work well across teams, coordinating with digital designers on control loops, with layout on physical implementation, and with characterization engineers on test plans

You stay current on process technology and circuit techniques, not because it is trendy but because it helps you design better blocks

The Team You'll Be Part Of

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