Applications Engineering, Sr Staff Engineer

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

Are you passionate about solving the toughest timing challenges at advanced nodes? Join Synopsys’ Signoff Static Timing Analysis (STA) team and work with industry-leading tools like PrimeTime, enabling the world’s most advanced semiconductor designs.

In this customer-facing role, you will act as a technical expert in timing signoff, collaborating with semiconductor companies to support Synopsys industry-leading PrimeTime signoff solutions for advanced node designs. You will work closely with customers, R&D, and product engineering teams to address complex timing challenges and drive methodology adoption.

This is a high-visibility, customer-facing role requiring strong technical depth, execution ownership, and cross-functional collaboration with Product and R&D teams.

What You'll Be Doing

Work directly with leading semiconductor companies to resolve complex timing closure and signoff challenges on advanced node designs, often under tight tapeout schedules

Debug critical timing issues including setup and hold violations, clock domain crossings, SI-induced timing failures, and variation-related signoff problems using PrimeTime

Guide customers through MMMC analysis, OCV/AOCV/POCV methodologies, and SI-aware timing flows tailored to 5nm and below process nodes

Collaborate with R&D and product engineering teams to reproduce customer issues, identify root causes, and drive tool enhancements or methodology improvements

Develop reference flows, automation scripts in Tcl and Python, and best practice documentation that customers can adopt and adapt to their specific design environments

Deliver technical training sessions, workshops, and live demos to customer design teams, covering PrimeTime capabilities, signoff methodologies, and advanced node considerations

Drive adoption of the latest PrimeTime technologies and signoff features by demonstrating value, building proof-of-concept flows, and supporting production deployment

The Impact You Will Have

Enable successful tapeouts for cutting-edge semiconductor designs by solving timing signoff challenges that would otherwise delay or block production schedules

Improve customer productivity and signoff quality by delivering automation scripts and methodology improvements that reduce manual effort and catch issues earlier

Influence PrimeTime product direction by channeling real customer pain points, design challenges, and feature requests directly to the R&D team

Build long-term technical partnerships with key accounts, becoming the trusted advisor they turn to when timing signoff gets complicated

Accelerate adoption of advanced PrimeTime features across the customer base, translating new capabilities into production value faster than competitors can respond

Reduce customer support escalations by proactively addressing methodology gaps, training design teams, and building reusable solutions

Shape industry best practices for timing signoff at advanced nodes by documenting what actually works in production, not just what works in theory

What You'll Need

Bachelor's degree in Electronics and Communication Engineering, plus Master's degree in VLSI, Embedded Systems, or Communication Systems

Strong hands-on experience with Synopsys PrimeTime for static timing analysis and signoff, including real production design exposure

Deep understanding of timing constraints using SDC, MMMC analysis frameworks, and variation-aware methodologies including OCV, AOCV, and POCV

Proven ability to debug complex timing issues such as setup and hold violations, clocking problems, signal integrity effects, and variability-driven failures

Proficiency in Tcl scripting for tool automation and flow development, Python or Perl scripting experience is a strong plus

Experience with advanced node designs at 5nm and below, including the unique timing challenges and signoff requirements at those geometries

Excellent communication skills and demonstrated ability to engage directly with customers, understand their technical challenges, and deliver solutions that work in their environment

Who You Are

You can walk into a customer meeting, listen to a timing problem described in five different ways by five different engineers, and identify the actual root cause before the meeting ends

You are comfortable saying "I don't know, but I will find out" when faced with an unfamiliar issue, and you follow through quickly with a real answer, not a deflection

You write automation scripts that other engineers actually want to use because they solve real problems and do not require a PhD to understand

You know when to escalate an issue to R&D and when to solve it with a methodology change, and you can explain that tradeoff clearly to both the customer and the product team

You treat customer tapeout schedules as your own deadlines, and you organize your work to unblock them even when it means jumping between three different accounts in one day

You can explain why a particular POCV derate is causing a timing violation to a senior design engineer without losing the technical nuance, and then explain the business impact to their manager in two sentences

The Team You'll Be Part Of

Leading the key customers and providing technical assistance on the Synopsys Signoff tools for Key customers in India.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.