R&D Engineering, Sr Engineer

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You are a passionate software engineer with electrical engineering background. You have learned electrical circuits, VLSI design, semiconductor physics or related areas, and proficient with C++ programming and designing efficient algorithms.

You are comfortable moving between electromagnetic theory and production C++ code. You can work on a quasi-static model in one day and spend another day optimizing a data structure that must handle billions of elements without falling over. When a foundry sends you a challenging new process modeling spec or a customer describes an accuracy problem, you do not panic, you dig in, reproduce it, and figure out where the model is missing.

Building things that must be right matters to you. Not approximately right for a demo, correct when someone tapes out a chip worth millions of dollars. You ask hard questions about accuracy versus runtime tradeoffs, and you care about both. You know that an extraction model that adds 10% runtime but catches a critical coupling issue is worth it.

At Synopsys, you will work on StarRC, the tool that sets the standard for parasitic extraction across the industry, and what you build will directly affect whether advanced designs close on schedule.

What You'll Be Doing

Research, design, and implement new transistor level extraction capabilities for StarRC, focusing on modeling accuracy for FinFET and gate-all-around devices at 3nm, 2nm, and beyond

Develop parasitic models for interconnect capacitance, inductance, and resistance using pattern-matching techniques and field solver methods

Design efficient algorithms and data structures in C++ that handle massive layout datasets while maintaining extraction accuracy and runtime performance

Apply computational electromagnetics principles to solve complex extraction problems for advanced process nodes

Collaborate with engineers across layout, simulation, timing, and physical verification teams to ensure StarRC integrates seamlessly into customer signoff flows

Work directly with foundries and customers to resolve extraction challenges in CPU designs, 3D IC systems, and advanced packaging structures

The Impact You Will Have

Enable accurate signoff for chips at the most advanced process nodes, directly affecting whether billion-dollar designs can tape out on schedule

Improve extraction runtime and capacity so customers can close timing on larger, more complex SoCs without sacrificing accuracy

Delivering capabilities that help foundries and design teams understand parasitic effects in new process technologies before they become yield problems

Strengthening StarRC's position as the gold standard extraction tool by solving problems competitors cannot

Help customers across CPU, AI accelerator, and memory design teams achieve first-pass silicon success by catching parasitic issues early

Shape the technical direction of extraction technology through direct collaboration with leading foundries and design houses

What You'll Need

MS or PhD in Electrical Engineering, Computer Science, or Computer Engineering with 1+ years of relevant EDA software development experience

Proficiency in C++ programming, algorithm design, and data structures for large scale software systems

Strong background in computational electromagnetics, including experience with full-wave or quasi-static EM modeling, Maxwell's equations, and numerical methods such as FEM, BEM, or MoM

Understanding how parasitic effects impact circuit performance and signoff, experience with LVS, extraction, or circuit simulation flows is a plus

Familiarity with field solver technology or transmission line analysis is a plus

Who You Are

You are a passionate software engineer with electrical engineering background. Graduate level research in electromagnetics a strong plus.

You are self-motivated, innovative and enjoy collaboration with similar technical minds to solve tough technical problems

You care about correctness at scale, an algorithm that works on a test case but crashes on a real customer design is not a solution

You are comfortable being wrong in a design review if it means the team catches a problem before it ships

You do not wait for perfect specs, when a foundry provides a spec, you identify the corner case scenarios, ask the right questions

The Team You'll Be Part Of

You will be a member of a high performing R&D team contributing to the development of StarRC, the EDA industry's gold standard for parasitic extraction. The team works on modeling physical effects for advanced process technologies, including FinFET at 7nm, 5nm, 3nm, 2nm, and beyond. You will collaborate closely with other product developers across layout design, simulations, timing, reliability verification, and physical verification.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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