Memory Layout Design Engineer

Incubent will work along our Registers and Memory Arrays and Memory data path layout and design engineers .

Based on the schematic shared you should be able to take it fwd and collaborate with circuit team etc to create best layout possible

Minimum Qualifications

· 5+ years of experience in Compiler/Custom Memory Layout design.

· Memory Leafcell layout library design from scratch including top level integration.

· Good knowledge on diAerent types of memory architectures. Good knowledge in optimized layout design for better performance.

· Sound knowledge & hands on experience in Finfet technology, layout design and DRC limitations. 3nm, 5 nm exposure required Proficient in physical verification flow & debug, like DRC, LVS, ERC, Boundary conditions.

· Proficient in Cadence Virtuoso layout editor and Calibre physical verification flow

Pay: $54,783.27-$145,890.36 per year

Work Location: In person