소프트웨어 엔지니어

Software Engineer (Optimization Algorithms)

About the Role

As an Algorithm Software Engineer, you will design and implement the combinatorial optimization engines of Axion's standard cell generation tool: transistor placement, in-cell routing, and design-rule-aware legalization. You will formulate layout generation as optimization problems (SAT / SMT / ILP / dynamic programming / heuristic search), build high-performance solvers in C++, and improve both solution quality and runtime on real industrial design rules.

Key Responsibilities

Design, implement, and tune placement and routing algorithms for transistor-level cell layout generation.

Formulate layout constraints (design rules, pin access, symmetry, track assignment) as SAT / SMT / ILP / CP models, or develop custom heuristic solvers.

Improve solver performance through search-space pruning, symmetry breaking, incremental solving, and parallelization.

Measure and improve quality of results (area, routability, DRC-clean rate) against hand-crafted reference layouts.

Build benchmark suites and regression harnesses to track QoR and runtime across solver and rule changes.

Work with layout and PDK engineers to translate foundry design rules into solver constraints.

Document algorithms and contribute to the tool's algorithmic roadmap.

Explore and implement first-order optimization methods (e.g., PDLP) and hardware-accelerated algorithms to scale solver capabilities for massive layout instances

Required Qualifications

BS / MS / PhD in Computer Science, Operations Research, Mathematics, or a related field with a focus on algorithms, optimization, or scheduling.

3+ years of experience developing optimization, scheduling, or search algorithms in production software, or a PhD with equivalent research engineering depth.

Strong C++ with attention to performance and memory; working Python.

Solid foundation in combinatorial optimization: ILP / SAT / SMT / CP, graph algorithms, dynamic programming, and local search.

Experience profiling and optimizing algorithm runtime and memory on large problem instances.

Treats solution quality, runtime, and hardware usage as first-class requirements.

Preferred Qualifications

Experience with EDA placement & routing, layout automation, or VLSI CAD algorithms.

Hands-on experience with industrial solvers (Gurobi, CPLEX, OR-Tools, Z3, MiniSat/Kissat), including model tuning.

Experience with parallel or distributed search, or solver portfolios.

Familiarity with modern large-scale linear programming techniques (e.g., PDLP) and their acceleration via parallel architectures or GPUs (e.g., CUDA).

Publications or contest results in optimization, SAT, or EDA (ISPD / ICCAD / DAC contests).

Familiarity with semiconductor design rules and standard cell layout.