STA Expert Engineer R&D (M/F)

About Eviden

Eviden is the Atos Group brand for hardware and software products with c. € 1 billion in revenue, operating in 36 countries and comprising four business units: advanced computing, cybersecurity products, mission-critical systems and vision AI. As a next-generation technology leader, Eviden offers a unique combination of hardware and software technologies for businesses, public sector and defense organizations and research institutions, helping them to create value out of their data. Bringing together more than 4,500 world-class talents and holding more than 2,100 patents, Eviden provides a strong portfolio of innovative and eco-efficient solutions in AI, computing, security, data and applications.

In the context of developing the next generations of our ASIC, we are looking for a STA expert engineer working on timing constraints definition (IP, bloc, top level) including also STA tool settings for sign-off.

Based in Paris area or Sophia-Antipolis, this position will be in R&D, in the team dedicated to the development of circuits integrated in systems designed by Bull-Atos Technologies. The team includes around 70 engineers, with a recognized expertise in development and integration of complex ASIC.

Main responsibilities

Timing constraints generation for ASIC flow (Using for synthesis, PNR and sign-off analysis)

In charge of timing analysis tool settings for timing closure and sign-off settings before tape-out

Perform STA Sign-off at top level

Work in close relationship with logical design, physical design and flow teams

Your profile

Bac + 5, Engineering degree or equivalent, with a specialization in micro-electronics and/or integrated circuits

At least 5 years of experience in timing constraints generation and timing convergence

Expertise in timing analysis tools Synopsys and/or Cadence (PrimeTime, Tempus Timing Sign-off Solution)

Familiarity with all methodologies of timing closure

Knowledge of ASIC design flow (RTL, DFT, equivalence checking and place and route flow)

Good experience of Clock Domain Crossing (CDC) timing issues and specifics timing exceptions (Multi cycle path, false path, max delay, min delay ….)

Good knowledge of modes/corners, OCV, AOCV and POCV concept, noise and cross-talk effects on timing in advanced process technology nodes (16nm and below)

Knowledge of low power techniques including clock gating, power gating and multi-voltage designs would be a plus

Very good experience in using TCL language

Good experience in Perl and/or Python languages

Good experience in using revision control tool (Git…)

Fluent English (collaboration with English-spoken engineers)

Let’s grow together.