Semiconductor Principal Design Engineer

Our vision is to transform how the world uses information to enrich life for all.

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

Position Overview

The Principal Design Engineer in Micron’s NVEG organization, you will be at the forefront of shaping the future of memory technology. In this role, you will lead the development, layout, and optimization of cutting-edge datapath circuits for next-generation NAND flash memory. You will act as a key technical leader, driving task forces and making strategic architectural decisions to achieve critical design targets such as unprecedented data rates and lower power consumption. By evaluating the trade-offs of emerging architectures, you will direct end-to-end implementation—from design planning and layout to silicon validation—ensuring project milestones are met while mentoring the next generation of engineering talent.

Responsibilities

Technical Ownership: Manage, design, and verify major IO/datapath blocks (e.g., input receiver, serializer, deserializer, clock distribution, equalizer, ZQ calibration, ONFI training features, and wave pipelines) to strictly meet performance specifications.

Layout & Optimization: Model layout parasitics and optimize signal quality. Conduct regular layout reviews to identify and execute on opportunities for area reduction and power efficiency improvements.

Cross-Functional Integration: Collaborate closely with project integration and other functional design teams to define and negotiate specifications for major block interfaces.

Silicon Bring-up & Yield: Partner with Product Engineering (PE) to define silicon experiments, drive silicon debugging, and propose architectural fixes to improve yield and performance.

Customer & Systems Alignment: Liaise with Applications Engineering (Apps) to evaluate the feasibility of introducing new specifications, balancing customer needs against design requirements and physical limitations.

Mentorship & Review: Document methodologies, present final results to expert panels and stakeholders, and actively mentor junior engineers to elevate the team's technical capabilities.

Minimum Qualifications

BS or MS in Electrical Engineering, or a related filed with 8+ years of relevant IC design experience

Advanced knowledge and deep intuitive understanding of high-speed IO circuit performance, power/area optimization, and top level chip architecture/floorplanning.

Proven track record in physical design flows, layout optimization, and parasitic extraction.

Demonstrated experience with high-speed interfaces for NAND and complex training/calibration features.

Preferred Qualifications

Hands-on experience in utilizing AI to improve design quality, workflow efficiency, or layout optimization.

Experience with DRAM interface(e.g. DDR4/5, LPDDR5/6, HBM3/3E/4) or other high speed industry standard interfaces.

Experience with signal/power integrity (SI/PI) and chip-level power delivery network(PDN) design and optimization

Comprehensive understanding of advanced CMOS device physics, device reliability mechanisms, BSIM modeling, and CMOS targets for high-speed IO operation.

About Micron Technology, Inc.

We are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all. With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities — from the data center to the intelligent edge and across the client and mobile user experience.

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