Sr Manager Digital Design Engineer

Job Summary:

The Director of Test Development will lead a team of highly skilled and talented Test and DfT (Design-for-Test) Engineers, with responsibility in defining and overseeing implementation of various DfT techniques and methods, focused on driving lowest cost of test across digital, analog, and mixed signal products. This role will be critical in defining requirements of future ATE tester roadmap, driven by product roadmaps and definitions.

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Responsibilities

Primary responsibilities

Drive state-of-the-art DfTs targeted for coverage, quality, maximum multi-site, and lowest cost-of-test (DfT Max).

Defining new ATE platforms to support roadmap products.

Defining and developing Test Method Libraries, thus enabling standardization and sameness across products and ATE platforms.

Co-own definition and development of DfT, Test Method, Test-plan, and validation / productization plans of all new IPs.

Developing Test Automation Tools to support various critical activities across NPDE and Cost Entitlement teams (Program Audits, Test Time Profilers, data-analysis tools, etc.).

Defining Test Flows across test insertions, driven towards best coverage and lowest cost-of-test.

Defining Process and Silicon Characterization requirements, for NPDE teams to follow during their product validation and execution.

Identify / document gaps, best practices, and lessons learned and feedback to Design, DfT, and PE NPDE / Cost Entitlement teams, to drive for better processes and test methods for future products. Good IC and test knowledge and background, across digital, analog, and mixed-signal, along with knowledge of ATE platforms, DfT strategies and test methods, and test instrumentation requirements for various Analog, Mixed-Signal, and Digital tests. Candidate must be familiar with protocols and industry standards for various IPs (high speed interfaces, analog and mixed-signal circuits, etc.). Prior experience working DfT, ATE Test Equipment for IC testing, and good hands-on knowledge across digital, analog, and RF is a must. Candidate must work closely with various cross-functional teams, including Design, Design DfT, and NPDE PE teams, with intent to direct, guide, and influence various aspects of product development in these shops.

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Qualifications

Drive state-of-the-art DfTs targeted for coverage, quality, maximum multi-site, and lowest cost-of-test (DfT Max).

Defining new ATE platforms to support roadmap products.

Defining and developing Test Method Libraries, thus enabling standardization and sameness across products and ATE platforms.

Co-own definition and development of DfT, Test Method, Test-plan, and validation / productization plans of all new IPs.

Developing Test Automation Tools to support various critical activities across NPDE and Cost Entitlement teams (Program Audits, Test Time Profilers, data-analysis tools, etc.).

Defining Test Flows across test insertions, driven towards best coverage and lowest cost-of-test.

Defining Process and Silicon Characterization requirements, for NPDE teams to follow during their product validation and execution.

Identify / document gaps, best practices, and lessons learned and feedback to Design, DfT, and PE NPDE / Cost Entitlement teams, to drive for better processes and test methods for future products. Good IC and test knowledge and background, across digital, analog, and mixed-signal, along with knowledge of ATE platforms, DfT strategies and test methods, and test instrumentation requirements for various Analog, Mixed-Signal, and Digital tests. Candidate must be familiar with protocols and industry standards for various IPs (high speed interfaces, analog and mixed-signal circuits, etc.). Prior experience working DfT, ATE Test Equipment for IC testing, and good hands-on knowledge across digital, analog, and RF is a must. Candidate must work closely with various cross-functional teams, including Design, Design DfT, and NPDE PE teams, with intent to direct, guide, and influence various aspects of product development in these shops.

#LI-RT1