Analog Layout Senior Engineer

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

Marvell’s Central Engineering (CE) team drives the development of advanced SoCs across a wide range of end markets, leveraging cutting-edge process technologies, analog mixed-signal design, and advanced packaging. Within CE, the AMS (Analog Mixed Signal) team is responsible for the layout design of high-speed SerDes IPs and other complex analog circuits, playing a key role in enabling Marvell’s next-generation semiconductor solutions.

This role is critical in ensuring high-performance analog circuits are accurately and efficiently implemented on silicon. As technology nodes advance, analog layout faces increasing challenges in complexity and variability—demanding innovative design approaches and sophisticated tooling. Marvell offers the ideal environment to explore these challenges, providing both breadth across engineering domains and depth within your specialization.

You’ll be part of a small, agile team making a big impact across Marvell’s product portfolio, including AI, cloud data center, storage, security, and networking.

What You Can Expect

Play a leading role in developing next-generation high-speed SerDes IPs as part of Marvell’s Central Engineering team, using advanced FinFET technologies to deliver best-in-class analog IPs.

Design and implement complex analog/mixed-signal layouts for SerDes, ADCs, PLLs, bandgap references, and LDOs across deep sub-micron CMOS, FinFET, and emerging GAA nodes using industry-standard tools (Cadence Virtuoso, Mentor).

Collaborate with circuit designers globally to translate schematics into efficient, high-performance layouts and drive end-to-end ownership from floor planning to tape-out.

Ensure physical verification closure by resolving DRC, LVS, ERC, and antenna violations; perform EMIR analysis and implement fixes for IR drop and electromigration.

Lead layout reviews, mentor junior engineers, and promote best practices, optimization techniques, and design rule compliance while fostering knowledge-sharing and process improvements.

Stay ahead of evolving technologies and tools, and develop automation scripts (Perl, Tcl, SKILL) to enhance productivity and consistency.

What We're Looking For

Education: BE/B.Tech or MS/M.Tech in Electrical/Electronics Engineering, Microelectronics, or related fields; 2–5 years of experience in high-speed analog/custom layout development.

Strong understanding of semiconductor process technologies, device physics, and layout effects in advanced nodes.

Proven experience in full-custom circuit layout and verification, including RC extraction, physical verification (DRC, LVS, ERC, DFM), and EMIR analysis.

Hands-on expertise in mixed-signal/analog/high-speed layouts (SerDes, ADC/DAC, PLL, etc.) across advanced FinFET technologies.

Proficiency with Cadence Virtuoso and industry-standard EDA tools; scripting skills (Perl, Tcl, SKILL) for automation are a plus.

Knowledge of critical layout techniques—matching, shielding, clock routing, power planning, ESD, and latch-up strategies.

Ability to own the full development cycle: floorplanning, layout, verification, and delivery.

Excellent communication skills to collaborate with global teams and provide clear status updates.

Self-motivated, adaptable, and eager to learn in a dynamic environment.

Additional Compensation and Benefit Elements

With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We’re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it’s like to work at Marvell, visit our Careers page.

Interview Integrity

To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.

These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.

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