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CPU Memory Design Engineer

Intel

USonsite$122k-$232k/yrPosted May 28, 2026

At a glance

Highlights

  • Hybrid work model
  • Competitive compensation
  • Stock bonus eligibility
  • Comprehensive benefits
  • RBA compliance

Heads up

  • Job details subject to change

Why this role might suit you

Designing high-performance memory circuits for Intel CPUs provides hands-on VLSI experience, competitive compensation, and access to comprehensive benefits within the client computing group.

Skills

cmosdigital-logicvlsimemory-designlow-powerebt-designsignal-integritycircuit-simulationcache-designppa-optimizationmemory-arrayip-designautomationmethodology-definition

About the role

Job Details:

Job Description:

The CPU Circuit Technology team is looking for a highly motivated and experienced individual to join our team as a CPU Memory Design Engineer. In this role, you will be responsible for designing, developing, and building full-custom as well as compiler-based SRAMs, Large Signal Arrays (custom multi-ported register file), ROMs, custom memories, digital circuits and Caches for Intel CPU and SOCs. You will be partnering with and leveraging domain experts across various areas of technology development to develop and deliver high-quality industry-leading memory technology collaterals and to drive circuit innovations that enable next generation high-performance, high-density, low-power embedded memory designs on advanced CMOS process technologies for Intel CPU and SOCs.

This will be a fast-paced dynamic environment where you will work in the high performance, low power CPU design team on a wide spectrum of circuit activities including, but may not be limited to: - Technical readiness, memory circuit design, characterization and simulations. - Cache design, critical path simulations and design custom blocks to meet stringent Power/Performance/Area constraints. - Memory path-finding activities and power, performance and area (PPA) optimization. - Memory bit-cell and complex periphery IC design and automation. - Memory array/IP design, memory circuit innovation - Methodology definition tasks as well as executing project schedules

Qualifications: Minimum Qualifications: - Bachelor's degree in Electrical Engineering, Computer Engineering, or a STEM-related field with 4+ years of experience; or Master's degree with 3+ years of experience; or PhD. - Proficiency in CMOS circuit design, digital logic optimizations, and circuit trade-offs for power, performance, and area. - Expertise in Very Large Scale Integration (VLSI) circuits and design methodologies.

Preferred Qualifications: - Experience in low-power implementation techniques and memory design. - Familiarity with circuit and layout trade-offs for optimized design. - Knowledge of EBB design tools, flows and methodologies, and signal integrity analysis. - Strong analytical and problem-solving skills, with the ability to prioritize tasks and work in dynamic environments.

Job Type: Experienced Hire

Shift: Shift 1 (United States of America)

Primary Location: US, Texas, Austin

Additional Locations:

Business group: The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them.

Posting Statement:

Position of Trust N/A

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range for jobs which could be performed in the US: $122,440.00-232,190.00 USD

The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. Job posting details (such as work model, location or time type) are subject to change.

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

Compensation

This Design Engineer role pays $122k-$232k/yr. Within typical range for design engineer roles in United States.

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