Senior Staff Analog Circuit Design Engineer - SerDes

Job Details:

Job Description:

The Role and Impact We are seeking a highly motivated and skilled Senior Staff Analog Circuit Design Engineer to contribute to the design, implementation, and validation of advanced analog and mixed-signal circuits for high-speed (112G and 224G) SerDes applications.

Key Responsibilities

Design and implement advanced analog and mixed-signal circuits for 112G and 224G SerDes applications

Participate in the definition, design, and verification of high-performance analog blocks and subsystems

Engage in technical discussions and contribute to design reviews

Conduct post-silicon validation and performance optimization

Provide guidance to layout engineers and mentor junior analog designers

Collaborate across disciplines with system architects, digital designers, and layout teams

Develop innovative designs as part of a highly experienced SerDes team focused on next-generation high-speed interconnect solutions

Core Competencies

Good communication and documentation skills, with a collaborative and proactive work style

Strong analytical thinking, hands-on debugging skills, and an eagerness to learn and share expertise within the team

Demonstrated ability to work effectively in cross-functional teams and contribute to technical reviews.

Excellent Communication Skills

Qualifications:

The Minimum qualifications are required to be initially considered for this position. Minimum qualifications listed below would be obtained through a combination of industry relevant job experience, internship experience and / or schoolwork/classes/research. The preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications

Bachelor’s degree in Electrical Engineering, Electronics Engineering, or in a STEM related field

2+ years of experience in analog/mixed-signal circuit design for high-speed SerDes or similar applications

Experience in one or more of the following domains: PLL, CDR, CTLE, DFE, ADC, LDO, Ref Gen, or Transmitter (TX) design

Experience with core analog design principles, including noise, linearity, matching, and stability

Experience with advanced FinFET CMOS process technologies

Experience with analog design and simulation tools such as Cadence Virtuoso/ADE, HSPICE, or equivalent

Preferred Qualifications

Ph.D. in Electrical Engineering, Electronics Engineering, or in a STEM related field

Experience with of transmitter and receiver design, CDR loops, and equalization techniques

Experience with next-generation high-speed standards such as PCIe 6.0, 800G Ethernet, or JESD

Experience with high-speed communication standards such as PCIe (Gen4/Gen5) and Ethernet (100G/400G)

Experience with Verilog-A modeling, MATLAB simulations, and automation scripting (e.g., Python, Tcl)

Experience with signal integrity concepts, channel modeling, and system-level link analysis

Job Type: Experienced Hire

Shift: Shift 1 (United States of America)

Primary Location: US, California, Santa Clara

Additional Locations: US, California, Folsom, US, Oregon, Hillsboro

Business group: The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.

Posting Statement:

Position of Trust N/A

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range for jobs which could be performed in the US: $164,470.00-361,480.00 USD

The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. Job posting details (such as work model, location or time type) are subject to change.

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.