SoC Physical Design Engineer

Job Details:

Job Description: The Role and Impact Intel's Devices Development Group is seeking a talented Physical Design Engineer to join our team in shaping the future of computing and semiconductor innovation. This role is integral to creating Client SoCs for next-generation laptops and desktop computers, driving Intel's mission to deliver world-changing technology that enriches lives globally. You will be instrumental in advancing Intel's leadership in SoC physical design, optimizing performance, power, and area to deliver best-in-class designs. Working with cutting-edge EDA tools and methodologies, you will help redefine how Intel builds SoCs and influence the broader semiconductor industry.

Key Responsibilities - Execute physical design implementation, including synthesis, place and route, clock tree synthesis, and floor planning, using industry-standard EDA tools such as Synopsys or Cadence. - Perform static timing analysis constraint generation, timing closure, and clock stamping to ensure high-quality SoC designs. - Conduct verification and signoff tasks, including formal equivalence verification, layout verification, and electrical rule checking. - Drive multiple power domain analysis using standard formats such as UPF or CPF to ensure power integrity. - Collaborate with process teams to optimize designs for power, frequency, and area. - Develop and enhance physical design methodologies and automation flows to improve efficiency and scalability. - Analyze results and recommend solutions to fix violations for current and future product architectures.

Qualifications: Minimum Qualifications - Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field with 6 or more years of experience; or Master's degree with 4 or more years of experience.

- Proficiency in physical design implementation, including synthesis, place and route, and clock tree synthesis. - Experience with static timing analysis constraint generation, timing closure, and clock stamping. - Familiarity with multiple power domain analysis using UPF or CPF formats. - Hands-on experience with Synopsys or Cadence tools for backend design and STA.

Preferred Qualifications - 5+ years of experience in backend design and/or STA. - Experience with product development and delivery on leading-edge process nodes. - Proven ability to collaborate in fast-paced team environments and solve complex problems. - Strong attention to detail with excellent organizational and communication skills. We invite you to join Intel and make your mark in advancing world-changing technology. Apply today to be a part of our journey shaping the future of computing and innovation.

Job Type: Experienced Hire

Shift: Shift 1 (India)

Primary Location: India, Bangalore

Additional Locations:

Business group: Silicon and Platform Engineering Group (SPE): Deliver breakthrough silicon and platform solutions that deliver industry-leading products today while also defining the next generation of computing experiences.

Posting Statement:

Position of Trust N/A

Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. Job posting details (such as work model, location or time type) are subject to change.

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.